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rev: 1.00 4/2003 1/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconducto r corp.. ntram is a trademark of samsung el ectronics co.. zbt is a trademark of inte grated device technology, inc. gs8645z18/36t-250/225/200/166/150/133 72mb pipelined and flow through synchronous nbt sram 250 mhz ? 133 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp commercial temp industrial temp product preview features ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? 2.5 v or 3.3 v +10%/ ? 10% core power supply ? 2.5 v or 3.3 v i/o supply ? user-configurable pipeline and flow through mode ? lbo pin for linear or interleave burst mode ? pin compatible with 2mb, 4mb, 8mb, and 16mb devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? zz pin for automatic power-down ? jedec-standard 100- lead tqfp package functional description the gs8645z18/36t is a 72mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/ write control inputs are ca ptured on the rising edge of the input clock. burst order control (lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and outp ut enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs8645z18/36t may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge triggered output regi ster during the access cycle and then released to the output driv ers at the next rising edge of clock. the gs8645z18/36t is implemented with gsi's high performance cmos technology and is available in a jedec- standard 100-pin tqfp package. -250 -225 -200 -166 -150 -133 unit pipeline 3-1-1-1 t kq tcycle 2.5 4.0 2.7 4.4 3.0 5.0 3.5 6.0 3.8 6.7 4.0 7.5 ns ns curr (x18) curr (x32/x36) 385 450 360 415 335 385 305 345 295 325 265 295 ma ma flow through 2-1-1-1 t kq tcycle 6.5 6.5 7.0 7.0 7.5 7.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns curr (x18) curr (x32/x36) 290 320 280 310 265 290 255 280 240 265 225 245 ma ma abcdef rwrwrw q a d b q c d d q e q a d b q c d d q e clock address read/write flow through data i/o pipelined data i/o flow through and pipelined nbt sr am back-to-back read/write cycles
rev: 1.00 4/2003 2/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview gs8645z18t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b ft v dd v dd v ss dq b dq b v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck w cke v dd v ss g adv a a a a a 4m x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.00 4/2003 3/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview gs8645z36t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c ft v dd v dd v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck w cke v dd v ss g adv a a a a a 2m x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.00 4/2003 4/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview 100-pin tqfp pin descriptions symbol type description a 0 , a 1 in burst address inputs; preload the burst counter a in address inputs ck in clock input signal b a in byte write signal for data inputs dq a1 -dq a9 ; active low b b in byte write signal for data inputs dq b1 -dq b9 ; active low b c in byte write signal for data inputs dq c1 -dq c9 ; active low b d in byte write signal for data inputs dq d1 -dq d9 ; active low w in write enable; active low e 1 in chip enable; active low e 2 in chip enable; active high. for self decoded depth expansion e 3 in chip enable; active low. for self decoded depth expansion g in output enable; active low adv in advance/load ; burst address counter control pin cke in clock input buffer enable; active low dq a i/o byte a data input and output pins dq b i/o byte b data input and output pins dq c i/o byte c data input and output pins dq d i/o byte d data input and output pins zz in power down control; active high ft in pipeline/flow through mode control; active low lbo in linear burst order; active low v dd in core power supply v ss in ground v ddq in output driver power supply nc ? no connect
rev: 1.00 4/2003 5/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview gs8645z18/36 nbt sram functional block diagram k sa1 sa0 burst counter lbo adv memory array e 3 e 2 e 1 g w b d b c b b b a ck cke d q ft dqa ? dqn k sa1? sa0? d q match write address register 2 write address register 1 write data register 2 write data register 1 k k k k k k sense amps write drivers read, write and data coherency control logic ft a 0 ?an
rev: 1.00 4/2003 6/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview functional details clocking deassertion of the clock enable (cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operati ons must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs (e 1 , e 2 and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables (e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contr ol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active, and the write input is sampled low at the rising edge of clock. the byte write enable inputs (b a , b b , b c, & b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. th e pipelined nbt sram provides double late write functionality, matching the write command versus data pipe line length (2 cycles) to the read comman d versus data pipeline length (2 cycles). a t the first rising edge of clock, enable, write, byte write(s), and address are registered. the data in associated with that addr ess is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to op erations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in that the write pipeline is one cy cle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second risin g edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 1.00 4/2003 7/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview synchronous truth table operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or wr ite, use the same control inputs. a deselect continue cycle can only be entered into if a dese- lect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active so no writ e operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined r ead cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles.
rev: 1.00 4/2003 8/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipeline and flow through read write control state diagram current state (n) next state (n+1) transition ? input command code key notes: 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes ,as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline and flow through read/write c ontrol state diagram w r
rev: 1.00 4/2003 9/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes: 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 1.00 4/2003 10/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes as indicated in the truth tables. flow through mode da ta i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipeline and flow th rough read write c ontrol state diagram
rev: 1.00 4/2003 11/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-t o-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded in to the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the lin ear burst order pin (lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst se quence is selected. see the tab les below for details. note: there is apull-up devices on the ft pin and a pull-down device on the zz pin, so thoseinput pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.00 4/2003 12/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview sleep mode during normal operation, zz must be pulled low, either by the user or by it?s internal pull down resistor. when zz is pulled hi gh, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally af ter 2 cycles of wake up time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exit ing sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on pin 14. not all vendors offer this option, however most mark pin 14 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep
rev: 1.00 4/2003 13/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an exte nded period of tim e, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c
rev: 1.00 4/2003 14/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v.
rev: 1.00 4/2003 15/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview note: these parameters are sample tested. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ? 40 25 85 c2 note: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 810pf input/output capacitance c i/o v out = 0 v 12 14 pf 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.00 4/2003 16/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 2 ua 2 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current (x36/x72) i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output leakage current (x18) i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
rev: 1.00 4/2003 17/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview operating currents notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. parameter test conditions mode symbol -250 -225 -200 -166 -150 -133 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current device selected; all other inputs v ih o r v il output open (x32/ x36) pipeline i dd i ddq 400 50 435 50 370 45 405 45 345 40 380 40 310 35 345 35 295 30 330 30 270 25 305 25 ma flow through i dd i ddq 295 25 320 25 285 25 310 25 270 20 295 20 260 20 285 20 245 20 270 20 230 15 255 15 ma (x18) pipeline i dd i ddq 360 25 395 25 335 25 370 25 315 20 350 20 285 20 320 20 275 20 310 20 250 15 285 15 ma flow through i dd i ddq 275 15 300 15 265 15 290 15 250 15 275 15 240 15 260 15 225 15 250 15 210 15 235 15 ma standby current zz v dd ? 0.2 v ? pipeline i sb 60 80 60 80 60 80 60 80 60 80 60 80 ma flow through i sb 60 80 60 80 60 80 60 80 60 80 60 80 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 100 115 95 110 90 105 85 100 85 100 80 95 ma flow through i dd 85 100 85 100 80 95 80 95 75 90 70 85 ma
rev: 1.00 4/2003 18/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above. parameter symbol -250 -225 -200 -166 -150 -133 unit min max min max min max min max min max min max pipeline clock cycle time tkc 4.0 ? 4.4 ? 5.0 ? 6.0 ? 6.7 ? 7.5 ? ns clock to output valid tkq ? 2.5 ? 2.7 ? 3.0 ? 3.5 ? 3.8 ? 4.0 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.2 ? 1.3 ? 1.4 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.2 ? 0.3 ? 0.4 ? 0.5 ? 0.5 ? 0.5 ? ns flow through clock cycle time tkc 6.5 ? 7.0 ? 7.5 ? 8.0 ? 8.5 ? 8.5 ? ns clock to output valid tkq ? 6.5 ? 7.0 ? 7.5 ? 8.0 ? 8.5 ? 8.5 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.5 ? 2.7 ? 3.0 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 2.7 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? 20 ? ns
rev: 1.00 4/2003 19/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview pipeline mode timing (nbt) write a read b suspend read c write d suspend1 write read e deselect thz tkqx tkq tlz ts tkqx tkq tkq th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd d(a) q(b) q(c) d(d) q(e) e ck cke e adv w b n a0?an dq
rev: 1.00 4/2003 20/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview flow through mode timing (nbt) write a read b suspend read c write d1 suspend1 write read e deselect thz tkqx tlz thz tkqx tkq th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd e d(a) q(b) q(c) d(d) q(e) ck cke e adv w b n a0?an dq
rev: 1.00 4/2003 21/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview tqfp package drawing d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 20.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ?? 0.10 lead angle 0 ? 7
rev: 1.00 4/2003 22/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview ordering information ? gsi nbt synchronous sram org part number 1 type package speed 2 (mhz/ns) t a 3 status 4m x 18 gs8645z18t-250 nbt pipeline/flow through tqfp 250/6.5 c 4m x 18 gs8645z18t-225 nbt pipeline/flow through tqfp 225/7 c 4m x 18 gs8645z18t-200 nbt pipeline/flow through tqfp 200/7.5 c 4m x 18 gs8645z18t-166 nbt pipeline/flow through tqfp 166/8 c 4m x 18 gs8645z18t-150 nbt pipeline/flow through tqfp 150/8.5 c 4m x 18 gs8645z18t-133 nbt pipeline/flow through tqfp 133/8.5 c 2m x 36 gs8645z36t-250 nbt pipeline/flow through tqfp 250/6.5 c 2m x 36 gs8645z36t-225 nbt pipeline/flow through tqfp 225/7 c 2m x 36 gs8645z36t-200 nbt pipeline/flow through tqfp 200/7.5 c 2m x 36 gs8645z36t-166 nbt pipeline/flow through tqfp 166/8 c 2m x 36 gs8645z36t-150 nbt pipeline/flow through tqfp 150/8.5 c 2m x 36 gs8645z36t-133 nbt pipeline/flow through tqfp 133/8.5 c 4m x 18 gs8645z18t-250i nbt pipeline/flow through tqfp 250/6.5 i 4m x 18 gs8645z18t-225i nbt pipeline/flow through tqfp 225/7 i 4m x 18 gs8645z18t-200i nbt pipeline/flow through tqfp 200/7.5 i 4m x 18 gs8645z18t-166i nbt pipeline/flow through tqfp 166/8 i 4m x 18 gs8645z18t-150i nbt pipeline/flow through tqfp 150/8.5 i 4m x 18 gs8645z18t-133i nbt pipeline/flow through tqfp 133/8.5 i 2m x 36 gs8645z36t-250i nbt pipeline/flow through tqfp 250/6.5 i 2m x 36 gs8645z36t-225i nbt pipeline/flow through tqfp 225/7 i 2m x 36 gs8645z36t-200i nbt pipeline/flow through tqfp 200/7.5 i 2m x 36 gs8645z36t-166i nbt pipeline/flow through tqfp 166/8 i 2m x 36 gs8645z36t-150i nbt pipeline/flow through tqfp 150/8.5 i 2m x 36 gs8645z36t-133i nbt pipeline/flow through tqfp 133/8.5 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8645z36t -166it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings
rev: 1.00 4/2003 23/23 ? 2003, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8645z18/36t-250/225/200/166/150/133 product preview 72mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8645zxx_r1 ? creation of new datasheet

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